1. Technical Field of the Invention
This invention relates generally to microcomputer architectures. More particularly, and not by way of limitation, the present invention is directed to a microcomputer array having a hyper-scalable, real-time monitoring and debug architecture in which several microcomputers are cascaded together by way of a cascaded instruction pipeline into a single, more powerful unit.
2. Description of Related Art
In the semiconductor industry today, there is a trend to implement custom systems on a chip. In such a system-on-a-chip, there is normally a processor and a number of peripherals that perform different system functions. For example, there may be a Universal Asynchronous Receiver-Transmitter (UART), a number of drivers, input/output processors (IOPs), and so on. In some cases there may be multiple processors along with hard logic that performs the different input/output (I/O) functions.
There are several problems with the existing approach for implementing custom systems-on-a-chip. One such problem is the long time to market. The IPs have to be designed and implemented in hardware to perform the specific hardware functions. This is a long and expensive process. The IPs then have to be integrated onto a single chip. Implementing the IPs in software is a possible solution to reduce the time required for hardware implementation. Historically, however, this has not been done because of several problems that developers were not able to overcome.
First is the problem of debugging the software. Each individual hardware function that is being performed in software must be simultaneously debugged in real time along with the coordinating software that makes everything work together. This is a daunting task that developers have often found takes longer than implementing the functions in hardware. Second is the problem of orchestrating the overall functioning of the system. Generally, a master processor must interact with and convey instructions to slave processors that perform the IP functions. In a first technique called Direct Memory Access (DMA), a bus arbitration process takes place between the master processor and one or more slaves. This is necessary in order to program the slaves to perform their intended functions, to configure them, and to communicate the results of the slave processing to the master. A second technique for communicating between the master processor and a slave processor is to use a mailbox scheme that, in one configuration, is performed by a serial shift register that is shifted between the master and the slave. In another mailbox configuration known as a parallel access mailbox, messages between the master and slave are passed by way of parallel registers or a dual-port memory.
A disadvantage of both of these techniques is that they require a significant amount of software overhead to implement them. To implement the hardware functions in software with one processor is a resource intensive operation. The operation takes up a lot of cycles, and overburdens the processor because of the software overhead involved.
In order to overcome the disadvantage of existing solutions, it would be advantageous to have an array of microcomputers and a method for implementing a system-on-a-chip that implements the peripheral functions in software, but does not overburden the nucleus processor with overhead software requirements. In addition, such an array would have a real-time simultaneous monitoring and debug capability. The present invention provides such an array and method.